Generally, a level translator or level shifter is provided between digital circuits to shift a voltage level of an input signal to a different output level. The digital circuits may require the different voltage levels for respective operations. For example, the voltage levels may define logic values of a signal (e.g., logic 1 or logic 0), and the different digital circuits may define logic values differently. For example, one circuit may require a voltage level greater than 3.3V for logic 1, while another circuit may require a voltage level greater than 5V for logic 1.
In integrated circuit (IC) design, each transistor of a semiconductor is able to withstand a certain maximum voltage across any two terminals of that transistor (e.g., source to drain, gate to source, gate to drain). The maximum voltage may be set by the semiconductor manufacturing process, for example. Typically, an IC is designed to include supply voltages that exceed the maximum voltage that individual transistors are able to handle. Accordingly, the voltage level must be reduced, for example, using level shifting circuits. However, a level shifting circuit creates a complex configuration requiring a constant current draw.
FIG. 1 is a circuit diagram illustrating an example of a conventional level shifter 100. The level shifter 100 is connected to a high voltage source which provides high level voltage Vhigh and a low voltage source which provides low level voltage Vlow. The level shifter 100 includes PMOS transistors 121 and 122 and NMOS transistors 111 and 112, which may be field effect transistors (FETs), for example. Transistor 121 includes a source connected to Vhigh, a gate connected to output Out1, and a drain connected to complementary output Out1b, and transistor 122 includes a source connected to Vhigh, a gate connected to Out1 and a drain connected to Out1b. Transistor 111 includes a source connected to Vlow, a drain connected Out1b and a gate connected to input In1, and transistor 112 includes a source connected to Vlow, a drain connected to Out1 and a gate connected to complementary input In1b. 
Assuming for purposes of illustration that Vlow=−3.3V, Vhigh=3.3V and In1 receives a digital input signal having a swing of −3.3V to 0V, Out1 would provide a digital output signal having a swing from 3.3V to −3.3V. If an inverter (not shown) were connected to Out1 with supplies at +3.3V and 0V, the output signal of the inverter would swing from 3.3V to 0V. In this manner, the input signal having a swing of −3.3V to 0V may be converted or shifted to an (inverted) output signal having a swing of 0V to 3.3V. However, in most IC processes, no transistor can handle more than 5V across any two terminals, for example. However, in the configuration of FIG. 1, each of the transistors (e.g., transistors 111, 112, 121 and 122) experiences 6.6V at least across its source to drain connections at some point during operation of the level shifter 100.